研究和发展高速、低功耗、面积小的模数转换器IP核对于系统芯片(SOC)设计具有非常重要的意义。折叠内插式ADC由于在速度、功耗和芯片面积等方面具有良好的特性而成为一个研究的热点。本文采用折叠内插结构，设计了一款基于标准CMOS工艺、1.8V电源电压、10位分辨率、100MS/s采样速率的高速ADC。由于折叠结构固有的倍频效应、较大的输入失调等限制因素，需要在折叠率和内插率的选择上进行合理的折衷，本文选择了3*3的级联折叠结构来实现9倍的折叠率，并在折叠过程中多次使用*2内插和*4内插。此外，本文还引入流水线技术和失调平均技术来克服折叠结构非理想因素的影响。由于流水线技术的使用，各级可以独立在各自的时钟相内完成工作，大大放宽了对折叠器，比较器等的带宽要求，而且流水线技术所需的非交叠时钟使得失调消除、分布式采样等技术可以被采用。本文采用SMIC 0.18μm 1P6M CMOS工艺，对电路进行了物理版图的实现，整个ADC有效芯片面积约为1.6mm*1.6mm。在1.8V电源电压、100MS/s采样速率、50MHz正弦波输入下进行仿真，ADC的SNDR达到56.79 dB，SFDR达到68.21dB，ENOB为9.1，功耗为120mW。

The research and development of analog to digital converter IP with high speed, low power and small area is of great significance in the field of SOC. With the excellent features in speed, power consumption and area, folding and interpolating analog to digital converter becomes a study hotspot in recent years. The research employs the folding and interpolating structure to design a high speed analog to digital converter with 1.8V power supply, 10bit resolution and 100MS/s sampling rate by the use of standard CMOS process. Because of the frequency-multiplier effect and the large input offset voltage, it is needed to carry on tradeoff between folding coefficient and interpolating coefficient carefully. The research employs 3*3 pipelined folding structure to achieve 9 folding coefficient, and employs *2 and *4 interpolating in the folding process. Besides, the research employs pipelining technique and interpolating error modification technique to overcome the frequency-multiplier effect. With the use of pipelining technique, the demand of comparators and folders is relaxed, and the techniques of offset cancellation and distributed T/H can be used.The research adopts SMIC 0.18μm 1P6M process to accomplish the circuit and layout design. The effective area of the chip is 1.6mm*1.6mm. At the situation of 1.8V power supply voltage, 100MS/s sampling rate and 50MHz sine wave input, the SNDR is 56.79dB, SFDR 68.21, and ENOB 9.1. The whole power consumption is 120mW.