模数转换器在模拟系统和数字系统之间扮演着无比重要的角色，是绝大多数电子系统中不可或缺的模块之一。随着数字化时代的发展，对信息处理系统的处理能力提出了更高的要求，未来对于ADC芯片的需求会逐日递增。由于逐次逼近型模数转换器（SAR ADC）有着结构简单、数字化程度高、面积小、功耗低、能很好适应制造工艺的变化等优点，使其成为ADC研究的热点结构。本文通过分析SAR ADC的研究成果与设计方法，提出了一种新型电容开关时序方案和一种数字后台校准技术，在此基础上设计了两款高效SAR ADC芯片。本文的主要工作与创新点如下：

1.本文通过对SAR ADC的基本结构、基础原理、实现方案等进行分析，研究了各个组成模块的结构及实现方法，并对实现过程中的非理想因素进行详细分析，为后期设计与优化提供理论指导。

2.本文通过研究降低电容开关能耗的多种方案，提出了一种基于拆分结构的新型电容开关时序方案。该方案通过对电容DAC（数模转换器）进行拆分，不仅有效降低了SAR ADC开关能耗，还大幅减小了电容DAC的面积。通过行为级仿真验证，与传统结构相比，该开关方案能够降低99.61%的开关能耗，节省87%的面积开销。

3.本文通过研究比较器输入参考噪声（IRN）的抑制方法，提出了一种基于积分时间调制和3-sample MV（the Majority Voting）相结合的降噪技术，有效降低了比较器输入参考噪声的影响，使SAR ADC的性能得到有效提升。

4.本文通过研究不同的电容失配校准技术，提出了一种数字后台校准（Digital Background Calibration）技术。该校准技术通过对DAC高分段的电容失配误差进行提取和校准，有效提高了SAR ADC的性能。基于TSMC 65 nm CMOS工艺设计的14位 SAR ADC流片测试结果表明：在采样速率为20 MS/s，奈奎斯特输入频率下，ENOB为12.8位，SNDR为78.8dB，SFDR为95.4dB，FoM_S为170.5dB。

本文通过仔细研究SAR ADC能效的提高方法，通过行为级建模仿真和流片对提出的方案进行验证，测试数据表明，本文中采用的设计方法能够有效提高SAR ADC的能效，达到了设计要求和研究目的。

Analog-to-digital converter plays an extremely important role between analog and digital systems, and is one of the indispensable modules in most electronic systems. With the development of the digital era, higher requirements are put forward for the processing capacity of the information processing system, and the demand for ADC chips will increase day by day in the future. The successive approximation A/D converter (SAR ADC) has the advantages of simple structure, high degree of digitalization, small area, low power consumption, and can well adapt to the changes of manufacturing process, making it a hot structure in ADC research. By analyzing the research results and design methods of SAR ADC, this thesis proposes a new capacitor switching scheme and a digital background calibration technology. On this basis, two efficient SAR ADC chips are designed. The main work and innovation of this thesis are as follows:

1. Through the analysis of the basic structure, basic principle and implementation scheme of SAR ADC, this thesis studies the structure and implementation method of each component module, and analyzes the non-ideal factors in the implementation process in detail, providing theoretical guidance for the later design and optimization.

2. This thesis proposes a novel capacitor switching scheme based on splitting structure by studying various schemes to reduce the energy consumption of capacitor switch. By splitting the capacitive DAC, this scheme not only effectively reduces the switching power consumption of SAR ADC, but also greatly reduces the area of the capacitive DAC (digital to analog converter). Compared with the traditional structure, the switching scheme can reduce the switching energy consumption by 99.61% and save 87% of the area cost through the behavioral simulation.

3. By studying the suppression method of comparator input reference noise (IRN), this thesis proposes a noise reduction technology based on the combination of integral time modulation and 3-sample MV (the Majority Voting), which effectively reduces the impact of comparator input reference noise and effectively improves the performance of SAR ADC.

4. This thesis proposes a digital background calibration technology by studying different capacitance mismatch calibration technologies. This calibration technology can effectively improve the performance of SAR ADC by extracting and calibrating the capacitance mismatch error of high segment in DAC. The test results of 14-bit SAR ADC based on TSMC 65 nm CMOS process design show that under the sampling rate of 20 MS/s and Nyquist input frequency, ENOB is 12.8-bit, SNDR is 78.8dB, SFDR is 95.4dB, FoM_S is 170.5dB.

This thesis carefully studies the methods to improve the energy efficiency of SAR ADC, and validates the proposed scheme through behavior-level modeling, simulation and tapering. The test data shows that the design method used in this thesis can effectively improve the energy efficiency of SAR ADC, and achieve the design requirements and research purposes.