随着现代国际局势愈发复杂，国防力量的提升刻不容缓。弹载雷达是目前各国研
究的重点对象，雷达导引头相当于给导弹加装“眼睛”，能够更精准打击目标。使用
数字波束形成技术处理相控阵雷达天线发射和接收的信号，可以提高雷达监测性能，
与传统雷达导引头相比优势更加明显，是未来精确制导武器的研究热点。基于以上背
景，为了研发对多波束信号实时采集处理系统，本文设计基于 FPGA 多通道雷达信号
处理机。
本文所设计的弹载雷达信号处理机，具有性能高、功耗低、且体积小的特点，包
含了信号产生和采集、数据传输、实时处理和数据存储等功能模块。在本设计中，接
口板主要负责通过不同的接口实现对各个分机进行控制和数据传输，该板卡选择
ZYNQ7000 系列的芯片作为主控芯片，其 FPGA 中内嵌 ARM 结构，方便逻辑代码设
计。两块采集板负责数据产生和采集，并对采集信号进行信号预处理，每块板卡包括
2 块 ADC 芯片，每块芯片两个通道，可以实现八通道实时采样处理。
本论文首先根据信号处理系统的设计要求，对雷达信号处理机系统中所用到的信
号采集模块 ADC 芯片和数据传输链路 JESD204B、串行 RapidIO、信号预处理算法相
关理论进行说明，根据设计指标进行系统方案设计。然后按照设计方案的内容，开始
进行硬件电路的设计。系统按照功能被划分为信号采集、信号产生、时钟、电源模块
等主要模块，本文对各模块所需要的器件参数进行分析，结合设计需求进行器件的选
型，然后进行模块原理图的设计，对电源模块进行功耗估计，根据 PCB 的相关技术，
对 PCB 板层进行规划设计，对板卡的布局进行合理的设计，之后进行布线，完成 PCB
的设计和制板焊接，并对最终板卡进行电路的测试。逻辑代码设计主要包括时钟芯片
寄存器参数配置、AD/DA 高速数据接口设计、串行 RapidIO 接口设计、主控系统设
计、信号预处理算法设计等，并对各个模块进行功能验证。然后根据系统设计方案，
首先，全面地测试雷达处理机系统的功能和性能，对测试结果进行分析，然后，对整
个雷达系统进行测试，验证雷达功能。分析测试结果证明本系统能够完成多通道雷达
信号处理的任务。在本论文的最后，对雷达处理机系统进行总结，对后续系统的维护
和升级提供思路。

As the modern international situation becomes more and more complex, the upgrading of 
national defense forces is a matter of urgency. The radar guidance head is equivalent to 
adding "eyes" to the missile, which can strike the target more accurately. The use of digital 
beamforming technology to process the transmit and receive signals of phased-array radar 
antennas can improve radar monitoring performance, and has more obvious advantages than 
traditional radar guidance heads, which is a hot spot for future research on precision-guided 
weapons. Based on the above background, in order to develop a real-time acquisition and 
processing system for multi-beam signals, this paper designs FPGA-based multi-channel 
radar signal processor.
The bullet radar signal processor designed in this paper is characterized by high performance, 
low power consumption and small size, and contains functional modules such as signal 
generation and acquisition, data transmission, real-time processing and data storage. In this 
design, the interface board is mainly responsible for the control and data transmission of 
each extension through different interfaces. The board chooses ZYNQ7000 series chip as 
the main control chip with embedded ARM structure in its FPGA, which is convenient for 
logic code design. The two acquisition boards are responsible for data generation and 
acquisition, and signal pre-processing of the acquired signals. Each board includes two ADC 
chips, each with two channels, which can realize eight channels of real-time sampling 
processing.
This paper first explains the relevant theories of the signal acquisition module ADC chip, 
data transmission link JESD204B, serial RapidIO, and signal preprocessing algorithm used 
in the radar signal processing system based on the design requirements of the signal 
processing system. The system scheme is designed according to the design indicators. Then, 
according to the design plan, start designing the hardware circuit. The system is divided into 
main modules according to its functions, such as signal acquisition, signal generation, clock, 
power supply module, etc. This article analyzes the device parameters required for each 
module, selects the device based on design requirements, designs the module schematic, 
estimates the power consumption of the power module, and plans and designs the PCB board 
layer based on relevant PCB technology. The layout of the board is designed reasonably, and 西安电子科技大学硕士学位论文
IV
then wiring is carried out, Complete PCB design and board soldering, and conduct circuit 
testing on the final board. The logic code design mainly includes the clock chip register 
parameter configuration, AD/DA high-speed data interface design, serial RapidIO interface 
design, master control system design, signal preprocessing algorithm design, and Functional 
verification of each module. Then, based on the system design plan, first, comprehensively 
test the functionality and performance of the radar processor system, analyze the test results, 
and then test the entire radar system to verify its functionality. The analysis and testing results 
prove that this system can complete the task of multi-channel radar signal processing. At the 
end of this paper, a summary of the radar processor system is provided to provide ideas for 
subsequent system maintenance and upgrades.

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