在复杂通信环境下，扩频信号在传输时，很容易受到强干扰的影响，而通常情况下绝大部分的干扰都可以认为是窄带干扰信号。在遇到强窄带干扰或者多窄带干扰，仅仅靠扩频增益来抑制干扰是不可行的。研究发现，解扩之前对干扰进行抑制，特别是对强单频干扰和窄带干扰进行抑制，可以大大改善扩频系统的性能。但是常规结构的陷波器在应对不同窄带干扰时，干扰抑制性能差异很大。针对上述问题，本文对高阶复数陷波器理论进行了深入的研究，并取得的主要研究成果为：1. 对陷波器的理论进行了研究。通过对变换域陷波以及时域FIR（Finite Impulse Response）和IIR（Infinite Impulse Response）几种陷波器基本原理的分析，提出了一种零极点配对的复数自适应陷波器算法。通过分析论证，以一阶陷波器为基本单元，给出了高阶矩阵型复数自适应陷波器的通用结构，分析了其陷波的基本原理，并给出高阶陷波器的迭代的具体步骤。本设计中的n阶复数陷波器，可以在不同信噪比下，有效抑制n个不同位置、不同强度的窄带干扰，同时对有用信号的损伤很小。2. 对陷波器的结构进行优化。根据该陷波器的结构特点，结合Matlab进行了仿真验证，对陷波器的关键因子及其对系统的影响做出了详尽的分析。步长 的大小，直接影响收敛速度，和收敛的稳定性；极点半径 的取值大小，决定了复数自适应陷波器的 带宽， 带宽在影响到陷波时的信号损伤，同时也会影响迭代的收敛速度；收敛点 的准确性直接影响到频率跟踪的准确性和稳态陷波性能。针对相应的关键因子本文提出了动定步长结合法，滑动窗平滑法以及分离参数法等算法。仿真结果表明，改进后的迭代算法收敛速度得到很大的提高，且收敛稳定性也大幅的改善。3. 完成了一阶、二阶、三阶复数陷波单元的FPGA（Filed Programmable Gate Array）设计。对相应的Matlab程序进行了量化，为了方便模块复用，即高阶陷波器可以由一阶陷波器模块直接例化得到，本文采用的是同步量化。根据量化后的程序，对陷波器进行了合理的模块划分，逐一进行了FPGA设计，最后分别在Modelsim仿真中给予验证。4. 完成了一阶、二阶、三阶陷波器FPGA设计的板级调试和验证。设计了两种方案对FPGA设计进行板级调试，先采用Signal_tap采样法，通对板级数据采样绘图法对陷波结果和中间数据进行验证，然后又运用了逻辑分析仪直接观察陷波前后效果，两种方案都验证了FPGA设计的正确性和有效性。

During transmission in a complex communications environment ,spread spectrum signal is susceptible to be interfered by strong signals, and most of which are usually considered to be narrowband interference.In face of strong narrowband interference or multiple narrowband interference, the spreading gain alone to suppress interference is not feasible. Studies indicated that the performance of the spread spectrum system can be improved a lot by suppressing interference before de-spreading,especially for strong single frequent interference or narrowband interference.However in response to different narrowband interference ,the interference suppression performance of notch filter with conventional structure varies very widely. To solve the problems above, high-order notch filter throries were deeply studied in this theise, the main research results obtained are as follows:1.Notch filter and the related theories are studied. Through research and analysis of transform-domain filter theories,time-domain of FIR and IIR filter theories, the high order complex notch filter with constrained poles and zeros algorithm is presented .Through the analysis of the first order notch filter, a general structure of the complex high-order matrix adaptive notch filter is promoted with the first order notch filter as the basic unit，and the fundamentals and the iteration steps of the high-order notch filter are also involved. For this design, the n-order complex notch filter can deal with n narrowband interference of different intensities at different positions in different SNR perfectly, while the effect on useful signal is very little.2. The structure of the notch filter is optimized. According to the structural features of the notch filter combined with Matlab simulation verification, several key factors and its impact on the system of the notch filter has been analyzed in detail. The step size greatly affects the convergence speed and convergence stability;the value of the pole radius directly determines the bandwidth of complex adaptive notch filter, which affects the notch filter performance and the iteration the convergence rate as well;the accuracy of the convergence point decide the accuracy of the frequency tack point and the steady results. To solved these problems , the dynamic-step and fixed-step combination method, the sliding window method and the separate parameters method are raised. Simulation show that the convergence speed of the iterative algorithm is greatly improved, and the convergence stability also increased a lot .3.The FPGA(Filed Programmable Gate Array) design of the first-order, second-order, and third-order notch filter is completed. For Matlab quantization, in order to reuse the modules , namely when we realize the high-order notch filter ,the modules of the first order notch filter module can be directly obtained , we quantified the program synchronously. Based on the quantified program ,we give a reasonable module division of the notch filter system, and for each module we conduct the FPGA design and verification with Modelsim simulation one by one.4. Complete the first-order, second-order, third-order notch board-level debugging and verification of FPGA design.Two verification approches are presented.First we use Signal_tap sampling method, by drawing on the board-level data of the final results and intermediate data for verification, and then another approach by logic analyzer direct observation is also promoted , Both of the methods confirmed the correctness and validity of the FPGA design.