在目前飞速发展的片上系统中，SoC上集成的IP核越来越多，结构越来越复杂，使得多核片上系统面临着巨大的调试压力。Intel基带芯片作为一种复杂的异构多核处理器系统，虽然内部实现了JTAG扫描技术和Coresight调试系统，但是已经不能满足对于庞大的芯片系统在单一点出现错误，需要抓住整个系统的现场状态，实现芯片内部资源完全可观测的需求。尤其是特定的内部存储、特殊的硬件加速器以及外设的寄存器值的可视化，对于快速定位故障位置，顺利开展调试工作愈发重要。

为解决上述问题，本文对不同的芯片内部资源进行研究，设计了一种多核处理器抓取故障现场的片上调试方法，通过对不同的模块以及子系统的设计，使得整个芯片系统可以进入特殊的调试模式并且保持冻结状态，最终通过唯一可活动的主处理器来获取整个芯片各个模块的状态信息，达到抓取故障现场的目的。论文的主要工作如下：首先基于四种不同处理器的调试模式和调试方法的分析对比，选定通过驱动外部调试接口的方式控制所有子系统的处理器进入调试模式，以避免对芯片现场产生干扰；其次，通过分析NoC与总线共同搭建的通信系统的特点，利用多核调试模块的输出信号驱动网络接口单元的Stall信号，使NoC不再接收来自所有其他发起者新的总线请求，同时清空NoC内部数据，使NoC处于空闲状态，达到截断芯片内部数据通路的目的；然后对于外设，采用TOPSPIN专利生成的外设支持特殊的悬挂模式，通过关闭外设主时钟的方式冻结外设，从而保证不对故障现场产生影响；最后，整个芯片的主处理器获得芯片唯一的访问权，实现故障现场的可视化，进一步开展调试工作，待锁定发生错误的模块后，就可以结合系统检测器具体分析错误模块相关的内部信号。

本文最终完成了基于基带芯片的故障定位系统的设计，运用UVM验证方法学编写了23个测试用例对本文的设计展开定向随机验证，通过覆盖率的收集来确保调试系统功能的完备性，最终验证结果表明代码覆盖率和功能覆盖率均达到100%，满足设计的要求。并且在流片之后，采用劳特巴赫硬件调试器的典型片上测试环境，对封装后的芯片进行了流片后测试，结合示波器对158个关键信号的状态进行近30次分组抽样监测，监测结果表明关键信号的状态正确，故障定位系统的功能达到预期。该调试系统的成功实现为调试人员提供了新的调试方案选择，大幅度降低了片上调试工作定位错误的时间。

In the current rapid development of system-on-chips, more and more IP cores are integrated into SoC and the structure is becoming more and more complex, which makes the multi-core SoC face huge debugging pressure. As a complex heterogeneous multi-core processor system, the Intel baseband chip implements JTAG scanning technology and Coresight debugging system inside the chip. However, these debugging methods can no longer meet the needs of a large-scale chip system at a single point of error, which need to grasp the on-site state of the entire system and achieve fully observable chip internal resources. In particular, the visualization of specific memory values and peripheral register values is increasingly important for quickly locating the location of a fault for debugging.

 

In order to solve the above problems, we have studied different internal resources of the chip and designed a method of on-chip debugging for multi-core processors to capture the fault scene. This debugging system enables the entire chip system to enter a special debugging mode and maintain a frozen state through the design of different modules and subsystems. And then, This system obtains the status information on each module of the entire chip through the only active main processor to achieve the purpose of capturing the fault scene. The main work of the paper are as follows:First of all, based on the analysis and comparison of the debugging modes and debugging methods of the four different processors, I chose to control all processors to enter the debugging mode by driving the external debugging interface to avoid affecting the state of the chip. Secondly, by analyzing the characteristics of the communication system formed by the NoC and the bus, I use the output signal of the multi-core debugging module to drive the Stall signal of the network interface unit, so that the NoC no longer receives new bus requests from other initiators and clears the internal data of the NoC. Such a design can keep the NoC in an idle state to intercept the internal data path of the chip. And then, I use TOPSPIN IP to generate peripherals that support special suspend mode. It freezes the peripherals by turning off the peripheral kernel clock to ensure that it does not affect the fault scene. Finally, the main processor of the chip obtain the unique access right of the chip to realize the visualization inside the chip. After the error module is locked, we can use the embedded system monitor to analyze the internal signals related to the error module.

 

I finally completed the design of the fault location system based on the baseband chip and used UVM verification methodology to write 23 testcases for directed functional test and random test of the design. The final code coverage and feature coverage collection results reached 100%, it shows that the debugging system meets the design requirements.After tapeout, I performed a post-silicon test on the packaged chip using the typical post-silicon tests environment of the Lauterbach hardware debugger and combined with an oscilloscope to monitor the status of 158 key signals for nearly 30 group samplings. The monitoring results show that the status of the key signals is correct and the function of the fault location system is as expected. The successful implementation of this debugging system provides debuggers with a new choice of debugging schemes and greatly reduces the time for on-chip debugging.

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