随着CMOS器件尺寸缩小至纳米领域，器件的性能指标正在接近物理极限，尤其是短沟道效应(SCE)越来越不容忽视。多栅器件作为新型结构器件，增强了栅控能力，有效的抑制了SCE。本文重点介绍了基于SOI器件技术的三栅FinFET器件，首先介绍FinFET工艺制作流程，接着通过ISE TCAD软件对三栅FinFET进行建模和仿真研究，取得的主要研究成果如下：首先研究了三栅FinFET I-V特性理论的基础，仿真研究不同三栅FinFET器件结构参数对漏电流的影响。由仿真结果可知：漏电流随着栅长减小而增大，随fin宽、fin高线性增大呈不完全线性增长。分析研究了三栅FinFET器件的阈值电压模型，仿真研究三栅FinFET器件结构参数对阈值电压的影响。结果显示，阈值电压随着栅长增大而增大，随着fin宽增大而减小，随着fin高增大而减小，与前面模型一致。研究了三栅FinFET结构对短沟道效应(SCE)的影响。介绍了亚阈值特性以及漏致势垒降低效应(DIBL)的基本理论。仿真研究三栅FinFET器件结构参数对亚阈值摆幅S和DIBL系数的影响。由仿真结果可知，亚阈值摆幅随着fin宽、fin高的减小而改善，即亚阈值特性得到了改善；同时DIBL系数随器件结构参数的变化与亚阈值摆幅S一致，即DIBL效应也随着fin宽及fin高的减小而改善。最后提出了一种源漏抬起FinFET(RSD FinFET)和源漏非均匀掺杂的三栅FinFET(AD FinFET)结构。仿真结果表明：RSD FinFET很好的增强了漏极电流，没有恶化短沟道效应；AD FinFET中漏极掺杂浓度相对源极越低，三栅FinFET器件中SCE改善的越好，但阈值电压会随着漏极掺杂浓度的降低而增大。

As the scaling of Complementary Metal-Oxide-Semiconductor Transistor (CMOS) approaches sub-nanometer regime, the performance of the device is moving to the physical limit, especially short-channel effects (SCE). Multiple-gate devices, as non-classical transisitors, can counteract SCE by improving the gate’s electrostatic control of the channel. This dissertation focuses on tri-gate FinFET based on SOI technology. Tri-gate FinFET is simulation through ISE TCAD modeling, the main research results obtained are as follows:Firstly, the simulation research of the influence of structure parameters on drain current is based on tri-gate FinFET I-V basic theory. It is found that the drain current increases as the gate length decreases, as fin height/fin width increase in incomplete linear relationship. Then, the threshold voltage model of tri-gate FinFET’s is analyzed and how structure parameters affect threshold voltage is studied. As results show, threshold voltage increases with increasing gate length and decreasing fin width and decreases with the increading fin height, which is consistent with the previous model.After that the research is focused on the effects of tri-gate FinFET structure on (SCE). The basis of subthreshold and drain-induced barrier lowering (DIBL) is introduced. Then, the simulation study is provided and the results show that subthreshold swing S is reduced with decreasing fin width/fin height--subthreshold characteristics are improved, while DIBL coefficient has the similar change rule with S, that is to say DIBL effects has been improved with decreasing fin width and fin height.Finally, new device structure raised source and drain FinFET(RSD FinFET) and asymmetric doped FinFET（AD FinFET）is proposed. The simulation study shows that the drain current increases in RSD FinFET. In AD FinFET, the smaller the concentration of drain doping, the more the SCE is improved. It should be paid to attention that threshold voltage increases with the decreasing drain doping concentration.