SRAM型FPGA的并行流水线、低功耗设计适用于卷积神经网络（Convolutional Neural Network，CNN）的加速，成为智能空间装备的深度学习领域重要支撑技术。但相比其他类型的硬件加速器，SRAM型FPGA对单粒子翻转（Single Event Upset，SEU）敏感性更高，面向卷积神经网络应用，研究FPGA单粒子翻转的检测与恢复方法，对促进深度学习类网络结构在空间辐射环境中高可靠应用有着重要意义。

现阶段，研究者大多使用回读的方式对FPGA中SEU现象进行检测，该方法是将回读的配置数据与黄金数据进行对比。而本文以SEU引起的电路信号异常为基础，提出一种基于关键信号的FPGA电路SEU检测和恢复方法，该方法可对CNN电路进行SEU检测。本文主要工作内容如下：

（1）为验证SEU现象会引起FPGA电路信号的异常变化，设计关键信号测试系统，对实际电路进行随机故障注入，观测电路中各个信号的数据变化。实验结果表明，FPGA中的SEU现象能够对电路信号数值变化产生影响，验证了关键信号测试系统的正确性和后文方法的可行性。

（2）基于FPGA电路模块内部逻辑关系、模块间连接关系和信号间数据传递关系，提出邻接信号比、最短路径比和信号连接比三个评价指标合成表征电路信号重要性的值，并据此选出关键信号。模拟故障注入实验结果验证了关键信号的有效性。

（3）提出基于关键信号的电路布设规则、异常检测规则和分析方法，使用现有方法恢复电路异常；评估关键信号在电路中布设的代价；为减少关键信号数据在传输过程中出现异常，以冗余思想设计关键信号防错结构。对关键信号分析方法和恢复策略进行验证，结果表明关键信号的分析和恢复策略是准确的；实验结果还表明，FPGA电路中SEU现象会引起电路功能异常、数据异常和故障掩盖现象。

（4）本课题选用LetNet-5作为卷积神经网络的代表结构，通过FPGA实现后，完成关键信号筛选、布设，并通过模拟故障注入，记录关键信号数据的变化，分析卷积神经网络电路中出现的故障类型和故障原因，具体分析LetNet-5电路中对SEU敏感的结构，对LetNet-5网络硬件电路提出了设计建议。实验结果表明，LetNet-5电路出现的异常多来自于数据路径中的异常，其中卷积层出现的异常次数较多。结果还表明，卷积层为LetNet-5电路中对SEU最为敏感的结构。

The parallel pipeline and low-power design of SRAM-based FPGAs is suitable for the acceleration of Convolutional Neural Network(CNN), which has become an important supporting technology in the field of deep learning of intelligent space equipment. However, compared with other types of hardware accelerators, SRAM-based FPGAs are more sensitive to Single Event Upsets(SEU), so the detection and recovery methods of FPGA single event upsets are studied for convolutional neural network applications. It is of great significance to promote the highly reliable application of deep learning network structure in space radiation environment.

 

At the current research stage, most researchers tend to use the readback method to detect the SEU phenomenon in FPGA, which is to compare the readback configuration data with the gold data. In this thesis, based on the circuit signal anomaly caused by SEU, proposes a new method for the detection and recovery of FPGA circuit SEU based on a key signal, which can be used to detect CNN circuit SEU. The research works of the thesis are as follows:

 

(1)In order to verify whether the SEU phenomenon will cause the abnormal changes of FPGA circuit signal, a key signal teste system is designed to inject random faults into the actual circuit to observe the data changes of each signal in the circuit. The experimental results show that the SEU phenomenon in FPGA will affect the circuit signal. In addition,the experiment verifies the correctness of the key signal test system and the feasibility of the following research method.

 

 (2) Based on the internal logic relationship of FPGA circuit modules, the connection relationship between modules and the data transmission relationship between signal, three evaluation indexes of adjacent signal ratio , shortest path ratio  and signal connection ratio  are proposed to characterize the importance of the  value circuit signal, and the key signal are selected accordingly. The simulation results of fault injection verify the effectiveness of the key signal.

 

(3) The circuit layout rules, anomaly detection rules and analysis methods based on key signal , using existing methods to recover circuit anomalies in the thesis; The cost of the key signal layout in the circuit is evaluated, and design of error proofing structure for key signal based on redundancy to reduce the abnormality of the key signal data in the transmission process. The key signal analysis method and recovery strategy are verified, and the results show that the key signal analysis and recovery strategy are accurate; It also show that the SEU phenomenon in FPGA circuit will cause abnormal circuit function, abnormal data and fault concealment.

 

(4) In this thesis, LetNet-5 is selected as the representative structure of convolutional neural network, after FPGA implementation, the key signal screening and layout are completed, and the changes of key signal data are recorded by simulating fault injection, the fault types and causes in convolutional neural network circuit are analyzed, and the structure sensitive to SEU in LetNet-5 circuit is analyzed in detail. The design suggestion of LetNet-5 network hardware circuit is put forward. The research results turn out that the anomalies of LetNet-5 circuit mostly come from the anomalies in the data path, and the number of anomalies in the convolution layer is more. It also shows that the convolution kernel calculation module is the most sensitive structure to SEU in the LetNet-5 circuit.

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